TMP93CS41 datasheet(89/248 Pages) TOSHIBA

89 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-87

3.6

Chip Select/Wait Controller, AM8/ AM16 pin

The TMP93CS40 and TMP93CS41 have a built-in chip select/wait controller used to control

chip select ( CS0 to CS2 pins), wait ( WAIT pin), and data bus size (8 or 16 bits) for any of the

three block address areas.

In addition, the AM8/ AM16 pin selects external data bus width.

3.6.1

AM8/ AM16 pin

(1) Usage in the TMP93CS40

Set this pin to “1”. After resetting, the CPU accesses the internal ROM with 16-bit

bus width. The bus width when the CPU accesses an external area is set by the chip

select/wait control register (described in section 3.6.3), P1CR and P1FC. (If this pin is

set to 1, that value will be ignored and the value set by register will be active.)

(2) Usage in the TMP93CS41

(2-1) When 16-bit bus width and 8-bit bus width are both used, or when 16-bit bus

width only is used:

Set this pin to “0”. Then the AD8 to AD15 or A8 to A15 pins of port 1 are fixed to

their A8 to A15 function compulsorily, and the values of P1CR and P1FC are

ignored.

The bus width when the CPU accesses an external area is set by the chip

select/wait control register described in section 3.6.2.

After a reset, 16-bit external program memory must be accessed before any

other memory is accessed.

(2-2) When 8-bit bus width only is used:

Set this pin to “1”. Then the AD8 to AD15 or A8 to A15 pins of port 1 are fixed to

their A8 to A15 function compulsorily, and the values of P1CR and P1FC are

ignored. The values of bit4 in <B0BUS>, <B1BUS>, or <B2BUS>, described in

section 3.6.3, are ignored and the bus width is fixed to 8 bits.

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