TMP93CS41 datasheet(91/248 Pages) TOSHIBA

91 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-89

3.6.3

Control Registers

Table 3.6.1 shows control registers.

One block of the address areas is controlled by each of the 1-byte CS/WAIT control

registers B0CS, B1CS, and B2CS.

(1) Master enable bits

Bit7 of the control registers (B0E, B1E, and B2E) are master bits used to specify

setting enable (1) or disable (0).

Resetting sets B0E and B1E to disable (0) and B2E to enable (1).

(2) CS/CAS waveform select

Bit5 of the control registers (B0CAS, B1CAS, and B2CAS) are used to specify the

waveform mode output from the chip select pin (from CS0 to CS2 , or from

CAS

). Setting these bits to 0 specifies CS0 to CS2 waveforms; setting them to 1

specifies

CAS

waveforms.

Resetting clears bits 5 to 0.

(3) Data bus size select

Bit4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus

size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1

accesses the memory in 8-bit data bus mode.

Changing data bus size depending on the access address is called dynamic bus sizing.

Table 3.6.2 shows the details of the bus operation.

This bit is changed by changing the state of the AM8/ AM16 pin.

(4) Wait control

Control register bits 3 and 2 <B0W1:0, B1W1:0, and B2W1:0> are used to specify the

number of waits. Setting these bits to 00 inserts a 2-state wait regardless of the WAIT

pin status. Setting them to 01 inserts a 1-state wait regardless of the WAIT status.

Setting them to 10 inserts a 1-state wait and samples the WAIT pin status. If the pin

is Low, inserting the wait maintains the bus cycle until the pin goes high. Setting them

to 11 completes the bus cycle without a wait, regardless of the WAIT pin status.

Resetting sets these bits to 00 (2-state wait mode).

TMP93CS41 데이터시트(PDF) 91 Page - Toshiba Semiconductor