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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS41 데이터시트(PDF) 103 Page - Toshiba Semiconductor |
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TMP93CS41 데이터시트(HTML) 103 Page - Toshiba Semiconductor |
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103 / 248 page  TMP93CS40/TMP93CS41 20004-02-10 93CS40-101 4. Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0 and INTT1) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. 5. Timer flip-flop The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output). Inverting is enabled or disabled by the timer flip-flop control register TFFCR<TFF1IE>. After a reset operation, the value of TFF1 is undefined. Writing “01” or “10” to TFFCR<TFF1C1:0> sets “0” or “1” to TFF1. Additionally, writing 00 to this bit inverts the value of TFF1. (Software inversion.) The value in TFF1 can be output to the TO1 pin (also used as P71). When using the TFF1 contents as the timer output, the timer flip-flop should be set by the port 7 function register P7FC beforehand. |
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