TMP93CS41 datasheet(121/248 Pages) TOSHIBA

121 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-119

Figure 3.8.4 Structure of Timer Registers 2

Memory addresses of the timer registers are as follows:

TREG2: 000026H (PWM timer 0)

TREG3: 000027H (PWM timer 1)

The timer register and register buffer are allocated to the same memory address. When

<DB2EN>

= 0, the same value is written to both the register buffer and timer register.

When

<DB2EN>

= 1, a value is written to the register buffer only.

is write-only and it cannot be read.

4. Comparator

This element compares the value in the up counter with the value in the timer register

(TREG2). When they match, the comparator outputs the match detect signal. A timer

interrupt (INTT2) is generated at compare and match if the interrupt select bit

<PWM0INT> of the mode register (P0MOD) is set to 1. In timer mode, the comparator

clears the up counter at compare and match. It also inverts the value of the timer flip-flop if

timer flip-flop invert is enabled.

5. Timer flip-flop

The value of the timer flip-flop is inverted by the match detect signal (comparator output)

of each interval timer or by 2n

− 1 overflow. The flip-flop value can be output to the timer

output pin TO2 (also used as P72).

Up counter

Timer register (TREG2)

Comparator

Internal data bus

TREG2 WR

PWM2

− 1 overflow

8-bit match detect

Write

Selector

<DB2EN>

Shift trigger

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