TMP93CS41 datasheet(144/248 Pages) TOSHIBA

144 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-142

The clock selected from among fFPH, fc/16, and fs is divided by 4 and input to this

prescaler. This selection is made by prescaler clock selection register SYSCR0<PRCK1:0>.

Resetting sets <PRCK1:0> to 00, selecting the fFPH clock input divided by 4.

The 16-bit timers 4 and 5 select among 3 clock inputs:

φT1, φT4, and φT16 among the

prescaler outputs.

This prescaler can be run or stopped by the timer operation control register

TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared to

zero and stops operation when <PRRUN> is set to “0”.

Resetting clears <PRRUN> to “0” and stops the prescaler.

When the IDLE1 mode (In which only the oscillator operates) is used, set

TRUN<PRRUN> to “0” to reduce the power consumption of the prescaler before the

“HALT” instruction is executed.

2. Up counter

The up counter is a 16-bit binary counter which counts up according to the input clock

specified by T4MOD<T4CLK1:0> register.

The alternatives for selecting the input clock include any one of the internal clocks

φT1,

φT4, and φT16 from the 9-bit prescaler (which is also used as an 8-bit timer), as well as the

external clock from the TI4 pin (which itself can also be used as the P80 or INT4 pin). When

reset, <T4CLK1:0> will be initialized to 00; this selects TI4 input mode. Counting or stop

and clear of the counter are controlled by timer operation control register TRUN<T4RUN>.

When clearing is enabled, up counter UC4 will be cleared each time it matches the timer

If clearing is disabled, the counter operates as a free-running counter.

3. Timer registers (TREG4 to TREG7)

These two 16-bit registers are used to set the interval time. When the value of up counter

UC4 matches the value set in this timer register, the comparator match detect signal will

be activated.

Setting data in both lower and upper registers are always needed. For example, either by

using a 2-byte data transfer instruction, or by using 1-byte data transfer instructions twice:

once for the lower 8 bits and once for the upper 8 bits in that order.

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