TMP93CS41 datasheet(171/248 Pages) TOSHIBA

171 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-169

The serial channel has buffer registers for temporarily storing transmitted or received data

during transmitting and receiving operations. This is so that transmitting and receiving

operations can be performed independently (Full duplex).

However, in I/O interface mode, the SCLK (Serial clock) pin is used for both transmitting and

receiving and the channel becomes half duplex.

The receiving data register is a double buffer structure that prevents the occurrence of

overrun errors and provides a margin of one frame before the CPU reads the received data. The

receiving data register stores the previously received data while the buffer register receives the

next frame.

By using CTS and RTS (There is no RTS pin, so any single port must be controlled by

software), it is possible to halt data transmission until the CPU finishes reading received data

wherever a frame is received (The handshake function).

In UART mode, an additional check function ensures that erroneous state bits caused by

noise do not cause receiving operations to start. The channel starts receiving data only when

the start bit is detected properly at least twice out of three samplings of the start bit.

When the transmission buffer becomes empty and requests the CPU to send the next

transmission data, or when data is stored in the receiving data register and the CPU is

requested to read the data, an INTTX (Transmit interrupt) or INTRX (Receive interrupt)

interrupt occurs. If an overrun error, parity error or framing error occurs during a receiving

operation, the flag SC0CR<OERR, PERR, FERR> is set.

The serial channel 0/1 has a special baud rate generator, which can set any baud rate by

dividing the frequency of the four clocks (

φT0, φT2, φT8, and φT32) from the 9-bit prescaler

(shared by the 8-bit/16-bit timers) by a value from 2 to 16.

In I/O interface mode, it is possible to input synchronous signals, as well as transmit or

receive data using an external clock.

3.11.1

Control Registers

The serial channels are controlled by three control registers: SC0CR, SC0MOD and

BR0CR. Transmitted and received data are stored in the register SC0BUF.

TMP93CS41 데이터시트(PDF) 171 Page - Toshiba Semiconductor