TMP93CS41 datasheet(191/248 Pages) TOSHIBA

191 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-189

1. Transmission

In SCLK output mode, 8-bit data and the synchronous clock are output from the

TXD0 pin and SCLK0 pin respectively, each time the CPU writes data to the

transmission buffer. When all data has been output, INTES0<ITX0C> will be set,

generating the INTTX0 interrupt.

Figure 3.11.20 Transmitting Operation in I/O Interface Mode (SCLK output mode)

(Channel 0)

In SCLK input mode, 8-bit data are output from the TXD0 pin when SCLK0 input

becomes active after data are written to the transmission buffer by the CPU.

When all data have been output, INTES0<ITX0C> will be set, generating the

INTTX0 interrupt.

Figure 3.11.21 Transmitting Operation in I/O Interface Mode (SCLK input mode)

(Channel 0)

Bit0

TXD0

Bit1

Bit6

Bit7

TXDSFT

SCLK0 output

Timing to write

transmission

data

ITX0C (INTTX0

interrupt request)

TXD0

TXDSFT

ITX0C (INTTX0

interrupt request)

SCLK0 input

(SCLKS

= 1: Falling edge mode)

Bit0

Bit1

Bit6

Bit7

Bit5

SCLK0 input

(SCLKS

= 0: Rising edge mode)

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