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TMP93CS41 데이터시트(PDF) 210 Page - Toshiba Semiconductor |
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TMP93CS41 데이터시트(HTML) 210 Page - Toshiba Semiconductor |
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210 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-208 3.13.3 Operation The watchdog timer generates interrupt INTWD after the detection time set in the WDMOD<WDTP1:0> and T45CR<QCU> registers has elapsed, and outputs a low level signal. The watchdog timer must be cleared to zero by software before an INTWD interrupt is generated. If the CPU malfunctions (Undergoes runaway) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter overflows and an INTWD interrupt is generated. The CPU detects malfunction (Runaway) from the INTWD interrupt and it is possible to return to normal operation using a recovery program. If the watchdog timer out pin is connected to the reset pins of peripheral devices, a CPU malfunction can also be acknowledged by these other devices. The watchdog timer restarts operation immediately after reset is released. The watchdog timer does not operate in IDLE1 or STOP mode. In RUN mode, the watchdog timer is operational. When the bus is released ( BUSAK = L), WDT continues counting. However, the function can be disabled when entering RUN or IDLE2 mode. The watchdog timer is enabled in IDLE2 mode, but the overflow interrupt is disabled. Disable the watchdog timer before entering IDLE2 mode. Example: 1. Clear the binary counter. WDCR ← 0100 1 1 1 0 Write the clear code (4EH). 2. Set the watchdog timer detecting time to 218/fSYS. WDMOD ← 101 − − − XX 3. Disable the watchdog timer. WDMOD ← 0 − − − − − X X Clear WDTE to “0”. WDCR ← 1011 0 0 0 1 Write disable code (B1H). 4. Set IDLE1 mode. WDMOD ← 0 − − − 1 0 X X Disable WDT and set IDLE1 mode. WDCR ← 1011 0 0 0 1 Executes halt command Set standby mode. 5. Set the STOP mode (Warm-up time: 216/fSYS) WDMOD ←− − − 1 0 1 X X Set the STOP mode. Executes halt command Execute HALT instruction. Set standby mode. |
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