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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS41 데이터시트(PDF) 230 Page - Toshiba Semiconductor |
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TMP93CS41 데이터시트(HTML) 230 Page - Toshiba Semiconductor |
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230 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-228 Timer control (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 QCU PG1T PG0T DB6EN DB4EN R/W R/W 0 0 0 0 0 1: Double buffer enable T45CR T4, T5 control 3AH Watchdog /warm-up timer control PG1 shift trigger 0: Timer 0, 1 1: Timer 5 PG0 shift trigger 0: Timer 0, 1 1: Timer 4 Double buffer of TREG6 Double buffer of TREG4 − W TREG6L 16-bit timer register 6 low 40H (Prohibit RMW) Undefined − W TREG6H 16-bit timer register 6 high 41H (Prohibit RMW) Undefined − W TREG7L 16-bit timer register 7 low 42H (Prohibit RMW) Undefined − W TREG7H 16-bit timer register 7 high 43H (Prohibit RMW) Undefined − R CAP3L Capture register 3 low 44H Undefined − R CAP3H Capture register 3 high 45H Undefined − R CAP4L Capture register 4 low 46H Undefined − R CAP4H Capture register 4 high 47H Undefined CAP3IN CAP34M1 CAP34M0 CLE T5CLK1 T5CLK0 W R/W 1 0 0 0 0 0 T5MOD 16-bit timer 5 source CLK and mode 48H 0: Soft capture 1: Don’t care Capture timing 00: Disable 01: T16 ↑ T17 ↑ 10: T16 ↑ T16 ↓ 11: TFF1 ↑ TFF1 ↓ 1: UC5 clear enable Source clock 00: T16 01: φT1 10: φT4 11: φT16 CAP4T6 CAP3T6 EQ7T6 EQ6T6 TFF6C1 TFF6C0 R/W W 0 0 0 0 1 1 TFF6 invert trigger 0: Trigger disable 1: Trigger enable T5FFCR 16-bit timer 5 flip-flop control 49H Inverted when the UC value is latched to CAP4 Inverted when the UC value is latched to CAP3 Inverted when the UC value matches TREG7 Inverted when the UC value matches TREG6 00: Invert TFF6 01: Set TFF6 10: Clear TFF6 11: Don’t care |
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