TMP93CS41 datasheet(244/248 Pages) TOSHIBA

244 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-242

(2) Points to note

, AM8/ AM16 pin

Fix these pins to VCC or GND unless changing voltage.

2. TEST1, TEST2 pin

Connect the TEST1 pin with the TEST2 pin. Do not connect to any other pins.

3. Reserved area in memory space

The 256 bytes of memory between FFFF00H and FFFFFFH cannot be used because

they are reserved.

Standby mode (IDLE1)

When IDLE1 mode (Oscillator operation only) is used, set TRUN<PRRUN> to 0 to

stop the prescaler before the HALT instruction is executed.

5. Warm-up counter

The warm-up counter operates when STOP mode is released even if the system is

using an external oscillator. As a result, a time equivalent warm-up time elapses from

input of the release request to output of the system clock.

6. Micro DMA (DRAM refresh mode)

When the bus is released ( BUSAK

= 0). DRAM refresh cannot be performed because

the micro DMA cannot access the bus.

7. Programmable pull-up/pull-down resistance

The programmable pull-up/pull-down resistors can be turned ON/OFF by the

program when the ports are used as input ports. When the ports are used as outputs,

they cannot be turned ON/OFF by the program.

The data registers (e.g., P2, P3,

…) are used for the pull-up/pull-down resistors

ON/OFF. Consequently read-modify-write instructions are prohibited.

8. Bus release function

Refer to the note about the bus release in 3.5 “Functions of Ports” as it describes the

state of the pins when the bus is released.

9. Watchdog timer

The watchdog timer starts operation immediately after the reset is released. When

the watch dog timer will not be used, disable it.

10. Watchdog timer

When the bus is released, neither internal memory nor internal I/O can be accessed.

However, the internal I/O continues to operate and hence, the watchdog timer

continues to run. Thus, take care when setting the bus release time and the detection

timer for the watchdog timer.

11. AD converter

The ladder resistor between the VREFH and VREFL pins can be cut by a program to

reduce power consumption. When standby mode is used, disable the resistor using the

program before the HALT instruction is executed. And set ADMOD2<SPEED1:0>

“00”.

12. CPU (Micro DMA)

Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control

registers in the CPU (like the transfer source address register (DMASn)).

13. POP SR instruction

Please execute POP SR instruction during DI condition.

14. Pin states in STOP mode

Open-drain output state. Input gate in operation. Set output to “L” or attach pull up

on pin so that the input gate stays constant.

TMP93CS41 데이터시트(PDF) 244 Page - Toshiba Semiconductor

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