TMP93CS44 datasheet(86/224 Pages) TOSHIBA

86 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-84

The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and

input to this prescaler. This is selected by prescaler clock selection register

SYSCR0<PRCK1:0>.

Resetting sets <PRCK1:0> to “00”, therefore fFPH/4 clock is input.

The 8-bit timer selects between 4 clock inputs:

φT1, φT4, φT16, and φT256 among the

prescaler output.

This prescaler can be run or stopped by the timer control register TRUN<PRRUN>.

Counting starts when <PRRUN> is set to “1”, while the prescaler is cleared to zero and

stops operation when <PRRUN> is set to “0”.

When the IDLE1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0”

to stop this prescaler before “HALT” instruction is executed.

2. Up counter

This is an 8-bit binary counter which counts up by the input clock pulse specified by

T10MOD and T32MOD.

The input clock of timer 0, 2 are selected from the external clock from TI0 (Only

timer 0) pin and the three internal clocks

φT1, φT4, and φT16, according to the set

value of T10MOD/T32MOD registers.

The input clock of timer 1 and 3 differs depending on the operation mode. When set

to 16-bit timer mode, the overflow outputs of timer 0 and 2 are used as the input clock.

When set to any other mode than 16-bit timer mode, the input clock is selected from

the internal clocks

φT1, φT16, and φT256 as well as the comparator output (Match

detection signal) of timer 0, 2 according to the set value of T10MOD and T32MOD

registers.

Example: When T10MOD<T10M1:0>

= 01, the overflow output of timer 0 becomes the

input clock of timer 1 (16-bit timer mode).

When T10MOD<T10M1:0>

= 00 and T10MOD<T1CLK1:0> = 01, φT1

becomes the input of timer 1 (8-bit timer mode).

Operation mode is also set by T10MOD and T32MOD registers. When reset, it is

initialized to T10MOD<T10M1:0>

= 00 and T32MOD<T32M1:0> = 00 whereby the up

counter is placed in the 8-bit timer mode.

The counting and stop and clear of up counter can be controlled for each interval

timer by the timer operation control register TRUN. When reset, all up counters will be

cleared to stop the timers.

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