TMP93CS44 datasheet(15/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-13

3.3

Dual Clock, Standby Function

Dual clock, standby control circuits consist of (1) System clock controller, (2) Prescaler clock

controller and (3) Standby controller.

The oscillator operating mode is classified to (a) Single clock mode (Only X1 and X2 pin), and

(b) Dual clock mode (X1, X2, XT1 and XT2 pin).

Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Figure 3.3.3

shows I/O registers. Table 3.3.1 shows the internal operation and system clock.

Figure 3.3.1 Transition Figure

The clock frequency input from X1, X2 pin is called fc and the clock frequency input from

XT1, XT2 pin is called fs. The clock frequency selected by SYSCR1<SYSCK> is called

system clock fFPH. The devided clock of fFPH is called system clock fSYS, and the 1 cycle of

fSYS, is called 1 state.

(a) Single clock mode transition figure

(b) Dual clock mode transition figure

Reset

NORMAL mode

(fc/gear value/2)

Release reset

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

IDLE1 mode

(Operates only osciIIator)

Instruction

Interrupt

Instruction

Interrupt

STOP mode

(Stops all circuits)

Instruction

Interrupt

Reset

NORMAL mode

(fc/gear value/2)

Release reset

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

IDLE1 mode

(Operates only oscillator)

Instruction

Interrupt

Instruction

Interrupt

STOP mode

(Stops all circuits)

Instruction

Interrupt

SLOW mode

(fs/2)

RUN mode

(Stops only CPU)

IDLE2 mode

(Stops CPU and AD)

IDLE1 mode

(Operates only oscillator)

Instruction

Interrupt

Instruction

Interrupt

Instruction

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