TMP93CS44 datasheet(24/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-22

3.3.2

Prescaler Clock Controller

The 9-bit prescaler provides a clock to 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5, and serial

interface 0, 1.

The clock input to the 9-bit prescaler is selected either fFPH, fc/16, or fs by

SYSCR0<PRCK1:0> register.

<PRCK1:0> register is initialized to “00” by resetting.

When the IDLE 1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0” to

stop 9 bit prescaler before “HALT” instruction is executed.

3.3.3

Internal Clock Pin Output Function

CLK pin outputs fSYS divided by 2 internal clock.

Outputs are specified by the clock output control register CKOCR<CLKEN>. Writing “1”

sets clock output, and writing “0” sets high impedance.

After reset, CKOCR<CLKEN> is depended on each product types. It is necessary to set

for each usage. Table 3.3.3 shows the value and operation after reset.

During reset, CLK pin is internally pulled up regardless of the value of <CLKEN>

Table 3.3.3 <CLKEN> and CLK Pin Operation after Reset

Type Number

CKOCR<CLKEN>

CLK Pin Operation

TMP93CS44

High impedance

TMP93CS45

fSYS/2 clock output

Note: To set <CLKEN>

= “0” and set CLK pin to high impedance, pull up externally to prevent

through current which follows to the input buffer of CLK pin.

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