TMP86FS28DFG datasheet(43/272 Pages) TOSHIBA

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Page 31

TMP86FS28DFG

2.3 Reset Circuit

The TMP86FS28DFG has four types of reset generation procedures: An external reset input, an address trap reset,

a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the

system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the

maximum 24/fc[s].

The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-

ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5

µs at 16.0 MHz) when

power is turned on.

Table 2-3 shows on-chip hardware initialization by reset action.

2.3.1 External Reset Input

The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.

When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-

age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-

ized.

When the RESET pin input goes high, the reset operation is released and the program execution starts at the

vector address stored at addresses FFFEH to FFFFH.

Figure 2-15 Reset Circuit

Table 2-3 Initializing Internal Status by Reset Action

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(FFFEH)

Prescaler and divider of timing generator

Stack pointer

(SP)

Not initialized

General-purpose registers

(W, A, B, C, D, E, H, L, IX, IY)

Not initialized

Jump status flag

(JF)

Not initialized

Watchdog timer

Enable

Zero flag

(ZF)

Not initialized

Output latches of I/O ports

Refer to I/O port circuitry

Carry flag

(CF)

Not initialized

Half carry flag

(HF)

Not initialized

Sign flag

(SF)

Not initialized

Overflow flag

(VF)

Not initialized

Interrupt master enable flag

(IMF)

Interrupt individual enable flags

(EF)

Control registers

Refer to each of control

Interrupt latches

(IL)

LCD data buffer

Not initialized

RAM

Not initialized

Internal reset

RESET

VDD

Malfunction

reset output

circuit

Watchdog timer reset

Address trap reset

System clock reset

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