TMP86FS28DFG datasheet(79/272 Pages) TOSHIBA

79 / 272 page

Page 67

TMP86FS28DFG

5.8 Port P7 (P70 to P77)

Port P7 is an 8-bit input/output port that can also be used for LCD segment output.

A reset initializes the output latch (P7DR) to “1”, the Pch control (P7OUTCR) to “0”, and the LCD output control

To use a pin in Port P7 as an input port, set P7DR to “1” and then set the corresponding bit in P7LCR and

P7OUTCR to “0”.

To use a pin in Port P7 as an LCD segment output, set the corresponding bit in P7LCR to “1”.

The output circuit of Port P7 can be set either as sink open-drain output (“0”) or CMOS output (“1”) individually

for each bit in P7OUTCR.

Port P7 has a separate data input register. The output latch state can be read from the P7DR register, and the pin

state can be read from the P7PRD register.

Note: An asterisk (*) indicates that either “1” or “0” can be set.

Figure 5-9 Port P7

Table 5-10 Register Programming for Port P7 (P70 to P77)

Function

Programmed Value

P7DR

P7OUTCR

P7LCR

Port input

“1”

“0”

Port “0” output

“0”

Set as

appropriate.

“0”

Port “1” output

“1”

“0”

LCD segment output

“1”

Data input (P7PRD)

Output latch read (P7DR)

STOP

OUTEN

P7OUTCRi input

Data output (P7DR)

P7OUTCRi

P7i

Note) i = 7~0

LCD data output

P7LCRi

P7LCRi input

Output latch

TMP86FS28DFG 데이터시트(PDF) 79 Page - Toshiba Semiconductor

TMP86FS28DFG 데이터시트(HTML) 79 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL