TMP86FS28DFG datasheet(56/272 Pages) TOSHIBA

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Page 44

3. Interrupt Control Circuit

3.7 External Interrupts

TMP86FS28DFG

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register

(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are dis-

abled using the interrupt enable register (EIR).

Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.

Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated

even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released.

External Interrupt Control Register

EINTCR

5432

(0037H)

INT1NC

INT0EN

INT4ES

INT3ES

INT2ES

INT1ES

(Initial value: 0000 000*)

INT1NC

Noise reject time select

0: Pulses of less than 63/fc [s] are eliminated as noise

1: Pulses of less than 15/fc [s] are eliminated as noise

R/W

INT0EN

P30/INT0 pin configuration

0: P30 input/output port

1: INT0 pin (Port P30 should be set to an input mode)

R/W

INT4 ES

INT4 edge select

00: Rising edge

01: Falling edge

10: Rising edge and Falling edge

11: H level

R/W

INT3 ES

INT3 edge select

0: Rising edge

1: Falling edge

R/W

INT2 ES

INT2 edge select

0: Rising edge

1: Falling edge

R/W

INT1 ES

INT1 edge select

0: Rising edge

1: Falling edge

R/W

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