TMP86FS28DFG datasheet(115/272 Pages) TOSHIBA

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Page 103

TMP86FS28DFG

8.2.3.3 Event Counter Mode

In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC11 pin.

Either the rising or falling edge of the input pulse is selected as the count up edge in TC11CR<TC11S>.

When a match between the up-counter and the TC11DRA value is detected, an INTTC11 interrupt is

generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at each edge

of the input pulse to the TC11 pin. Since a match between the up-counter and the value set to TC11DRA

is detected at the edge opposite to the selected edge, an INTTC11 interrupt request is generated after a

match of the value at the edge opposite to the selected edge.

Two or more machine cycles are required for the low-or high-level pulse input to the TC11 pin.

Setting TC11CR<ACAP11> to “1” captures the up-counter value into TC11DRB with the auto capture

function. Use the auto-capture function in the operative condition of TC11. A captured value may not be

fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a

capture enabled condition. Since the up-counter value is captured into TC11DRB by the source clock of

up-counter after setting TC11CR<ACAP11> to "1". Therefore, to read the captured value, wait at least

one cycle of the internal source clock before reading TC11DRB for the first time.

Figure 8-12 Event Counter Mode Timing Chart

Table 8-4 Input Pulse Width to TC11 Pin

Minimum Pulse Width [s]

NORMAL1/2, IDLE1/2 Mode

SLOW1/2, SLEEP1/2 Mode

High-going

23/fc

23/fs

Low-going

23/fc

23/fs

At the

rising edge

(TC11S = 10)

INTTC11

interrput request

TC11 pin Input

Up-counter

TC11DRA

Timer start

Match detect

Counter clear

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