TMP86FS28DFG datasheet(190/272 Pages) TOSHIBA

190 / 272 page

Page 178

13. Asynchronous Serial interface (UART0 )

13.9 Status Flag

TMP86FS28DFG

Figure 13-7 Generation of Overrun Error

Note:Receive operations are disabled until the overrun error flag UART0SR<OERR> is cleared.

13.9.4 Receive Data Buffer Full

Loading the received data in RD0BUF sets receive data buffer full flag UART0SR<RBFL> to "1". The

UART0SR<RBFL> is cleared to “0” when the RD0BUF is read after reading the UART0SR.

Figure 13-8 Generation of Receive Data Buffer Full

Note:If the overrun error flag UART0SR<OERR> is set during the period between reading the UART0SR and read-

ing the RD0BUF, it cannot be cleared by only reading the RD0BUF. Therefore, after reading the RD0BUF,

read the UART0SR again to check whether or not the overrun error flag which should have been cleared still

remains set.

13.9.5 Transmit Data Buffer Empty

When no data is in the transmit buffer TD0BUF, that is, when data in TD0BUF are transferred to the transmit

shift register and data transmit starts, transmit data buffer empty flag UART0SR<TBEP> is set to “1”. The

UART0SR<TBEP> is cleared to “0” when the TD0BUF is written after reading the UART0SR.

Final bit

Stop

Shift register

xxxx0*

1xxxx0

yyyy

xxx0**

RXD0 pin

UART0SR<OERR>

INTRXD0 interrupt

After reading UART0SR then

RD0BUF clears OERR.

RD0BUF

UART0SR<RBFL>

Final bit

Stop

Shift register

xxxx0*

1xxxx0

xxxx

yyyy

xxx0**

RXD0 pin

UART0SR<RBFL>

INTRXD0 interrupt

RD0BUF

After reading UART0SR then

RD0BUF clears RBFL.

TMP86FS28DFG 데이터시트(PDF) 190 Page - Toshiba Semiconductor

TMP86FS28DFG 데이터시트(HTML) 190 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL