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TMP86FS28DFG 데이터시트(PDF) 206 Page - Toshiba Semiconductor

부품명 TMP86FS28DFG
상세설명  8 Bit Microcontroller
PDF  272 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS28DFG 데이터시트(HTML) 206 Page - Toshiba Semiconductor

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Page 194
16. LCD Driver
16.2 Control
TMP86FS28DFG
16.2 Control
The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver’s display is enabled using
the EDSP.
Note 1: When <BRES>(Booster circuit control) is set to “0”, VDD ≥ V3 ≥ V2 ≥ V1 ≥ VSS should be satisfied.
When <BRES> is set to “1”, 5.5 [V]
≥ V3 ≥ VDD should be satisfied.
If these conditions are not satisfied, it not only affects the quality of LCD display but also may damage the device due to
over voltage of the port.
Note 2: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set LCDCR<DUTY> to "10" or "11"
when the booster circuit is enable.
Note 3: Do not set SLF to “10” or “11” in SLOW1/2 modes.
Note 4: Do not set VFSEL to “11” SLOW1/2 modes.
LCD Driver Control Register
LCDCR
(0FD9H)
76
543
21
0
EDSP
BRES
VFSEL
DUTY
SLF
(Initial value: 0000 0000)
EDSP
LCD Display Control
0: Blanking
1: Enables LCD display (Blanking is released)
R/W
BRES
Booster circuit control
0: Disable (use divider resistance)
1: Enable
VFSEL
Selection of boost frequency
NORMAL1/2, IDLE/1/2 mode
SLOW1/2,
SLEEP0/1/2 mode
DV7CK = 0
DV7CK = 1
00
fc/213
fs/25
fs/25
01
fc/211
fs/23
fs/23
10
fc/210
fs/22
fs/22
11
fc/29
fc/29
–
DUTY
Selection of driving methods
00: 1/4 Duty (1/3 Bias)
01: 1/3 Duty (1/3 Bias)
10: 1/2 Duty (1/2 Bias)
11: Static
SLF
Selection of LCD frame fre-
quency
NORMAL1/2, IDLE/1/2 mode
SLOW1/2,
SLEEP0/1/2 mode
DV7CK = 0
DV7CK = 1
00
fc/217
fs/29
fs/29
01
fc/216
fs/28
fs/28
10
fc/215
fc/215
–
11
fc/213
fc/213
–



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