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ADBMS1818ASWAZ-R7 데이터시트(PDF) 10 Page - Analog Devices

부품명 ADBMS1818ASWAZ-R7
상세설명  18-Cell Battery Monitor with Daisy Chain Interface
PDF  92 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADBMS1818ASWAZ-R7 데이터시트(HTML) 10 Page - Analog Devices

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Data Sheet
ADBMS1818
SPECIFICATIONS
analog.com
Rev. B | 10 of 92
ISOSPI TIMING SPECIFICATIONS
See Figure 86.
Table 10.
Parameter
Test Conditions/Comments
Min
Typ
Max
Units
SCK Falling Edge to SDO Valid (t8)1
Apply over the full specified temperature range
60
ns
SCK Rising Edge to Short ±1 Transmit (t9)
Apply over the full specified temperature range
50
ns
CSB Transition to Long ±1 Transmit (t10)
Apply over the full specified temperature range
60
ns
CSB Rising Edge to SDO Rising (t11) 1
Apply over the full specified temperature range
200
ns
Data Return Delay (tRTN)
Apply over the full specified temperature range
325
375
425
ns
Chip-Select Daisy-Chain Delay (tDSY(CS))
Apply over the full specified temperature range
120
180
ns
Data Daisy-Chain Delay (tDSY(D))
Apply over the full specified temperature range
200
250
300
ns
Data Daisy-Chain Lag (vs. Chip Select) (tLAG)
= (tDSY(D) + t1/2PW(D)) – (tDSY(CS) + t1/2PW(CS)), apply over the full
specified temperature range
0
35
70
ns
Chip Select High to Low Pulse Governor (t5(GOV)) Apply over the full specified temperature range
0.6
0.82
µs
Data to Chip-Select Pulse Governor (t6(GOV))
Apply over the full specified temperature range
0.8
1.05
µs
isoSPI Port Reversal Blocking tBLOCK Window
Apply over the full specified temperature range
2
10
µs
1 These specifications do not include rise or fall time of SDO. Although fall time (typically 5 ns due to the internal pull-down transistor) is not a concern, the rising edge
transition time (tRISE) is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time
requirements of the microcontroller unit (MCU).



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