FS32K142HAT0MLHT datasheet(5/84 Pages) NXP

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Crossbar switch (AXBS-Lite)

eDMA

DMA

MUX

SW-DP

Serial Wire

AWIC

Clock

LPO

128 kHz

generation

Peripheral bus controller

CRC

WDOG

LPIT

LPI2C

FlexIO

Low Power

Timer

12-bit ADC

TRGMUX

LPUART

LPSPI

FlexCAN

FlexTimer

PDB

LPIT

RTC

CMP

8-bit DAC

ERM

CMU

GPIO

Flash memory

controller

Data flash

memory

FlexRAM/

SRAM2

Code flash

memory

IO PORT

NVIC

PPB

MTB+DWT

BPU

AHB-AP

Arm Cortex M0+

Peripherals present

on all S32K devices

Peripherals present

on selected S32K devices

Key:

Device architectural IP

on all S32K devices

(see the "Feature Comparison"

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned

different access rights to each protected memory region. The Arm M0+ core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the S32K1xx Series Reference Manual.

section)

IO PORT

CSEc

System MPU1

SOSC

4-40 MHz

SIRC

8 MHz

FIRC

48 MHz

EIM

SRAM2

Figure 2. High-level architecture diagram for the S32K11x family

2 Feature comparison

The following figure summarizes the memory, peripherals and packaging options for the

S32K1xx devices. All devices which share a common package are pin-to-pin compatible.

NOTE

Availability of peripherals depends on the pin availability in a

particular package. For more information see IO Signal

Feature comparison

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

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