LAN9252SLASHML datasheet(243/329 Pages) MICROCHIP

243 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 243

LAN9252

12.14.25 ESC CONFIGURATION REGISTER

Note 11:

The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu-

rable Registers," on page 201 for additional information.

Note:

This register is initialized from the contents of the EEPROM. The EEPROM settings for Enhanced Link

detection (bits 6,5,4,1) are only taken at the first EEPROM loading after power-on reset. Changing the

EEPROM and manually reloading it will not affect the Enhanced link detection enable status, even if the

EEPROM could not be read initially.

Offset:

0141h

Size:

8 bits

Bits

Description

ECAT

Type

PDI

Type

Default

RESERVED

Enhanced Link Port 2

Disabled (if bit 1 = 0)

Enabled

Note 11

Enhanced Link Port 1

Disabled (if bit 1 = 0)

Enabled

Note 11

Enhanced Link Port 0

Disabled (if bit 1 = 0)

Enabled

Note 11

Distributed Clocks Latch In Unit

Disabled (power saving)

Enabled

Note:

This bit has no affect.

Distributed Clocks SYNC Out Unit

Disabled (power saving)

Enabled

Note:

This bit has no affect.

Enhanced Link Detection All Ports

Disabled (if bits [7:4] = 0)

Enabled all ports

Note 11

Device Emulation

(control of AL Status Register)

AL Status Register must be set by PDI

AL Status Register set to value written to AL Control Register

Note:

The value programmed should be 1 for Digital I/O

mode and 0 for applications with a host controller.

Note 11

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