LAN9252SLASHML datasheet(65/329 Pages) MICROCHIP

65 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 65

LAN9252

Change on Read Registers and FIFOs

FIFOs or “Change on Read” registers, are updated at the end of the read cycle.

For 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word.

Change on Read Live Register Bits

As described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul-

tiple bits that span across BYTES or WORDS are also locked for 16 and 8-bit accesses. Although a H/W event that

occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the

end of the read cycle and the H/W event would be lost.

In order to prevent this, the individual CSRs defer the H/W event update until after the read or multiple reads.

Some registers support polling during reset or device initialization to determine when the device is accessible. For these

registers, only one read may be performed without the need to read the other WORD or BYTEs. The same BYTE or

WORD of the register may be re-read repeatedly.

A register that is 16 or 8-bit readable or readable during reset or device initialization, is noted in its register description.

9.4.2.3

Host Endianness

The device supports big and little endian host byte ordering based upon the endianness select that is latched during the

address latch cycle. When the endianness select is low, host access is little endian and when high, host access is big

endian. In a typical application the endianness select is connected to a high-order address line, making endian selection

address-based. This highly flexible interface provides mixed endian access for registers and memory for both PIO and

host DMA access.

All internal busses are 32-bit with little endian byte ordering. Logic within the Host Bus Interface re-orders bytes based

on the appropriate endianness bit, and the state of the least significant address bits.

Data path operations for the supported endian configurations and data bus sizes are illustrated in FIGURE 9-1: Little

Endian Ordering on page 66 and FIGURE 9-2: Big Endian Ordering on page 67.

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