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LAN9252/ML 데이터시트(PDF) 251 Page - Microchip Technology

부품명 LAN9252/ML
상세설명  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML 데이터시트(HTML) 251 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 251
LAN9252
12.14.33 ECAT EVENT REQUEST REGISTER
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
0210h-0211h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:8
RESERVED
RO
RO
00h
7
SyncManager Status Mirror
This bit mirrors the value of the SyncManager Channel 3 Status.
0:
No Sync Channel 3 Event
1:
Sync Channel 3 Event Pending
RO
RO
0b
6
SyncManager Status Mirror
This bit mirrors the value of the SyncManager Channel 2 Status.
0:
No Sync Channel 2 Event
1:
Sync Channel 2 Event Pending
RO
RO
0b
5
SyncManager Status Mirror
This bit mirrors the value of the SyncManager Channel 1 Status.
0:
No Sync Channel 1 Event
1:
Sync Channel 1 Event Pending
RO
RO
0b
4
SyncManager Status Mirror
This bit mirrors the value of the SyncManager Channel 0 Status.
0:
No Sync Channel 0 Event
1:
Sync Channel 0 Event Pending
RO
RO
0b
3
AL Status Event
0:
No change in AL Status
1:
AL Status Change
Note:
This bit is cleared by reading the AL Status Register
from ECAT.
RO
RO
0b
2
DL Status Event
0:
No change in DL Status
1:
DL Status Change
Note:
This bit is cleared by reading the ESC DL Status Reg-
ister from ECAT.
RO
RO
0b
1
RESERVED
RO
RO
0b
0
DC Latch Event
0:
No change on DC Latch Inputs
1:
At least one change on DC Latch Inputs
Note:
This bit is cleared by reading the DC Latch event
times from ECAT for ECAT controlled Latch Units, so
that the LATCH0 Status Register/LATCH1 Status
Register indicates no event.
RO
RO
0b



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