LAN9252SLASHML datasheet(142/329 Pages) MICROCHIP

142 / 329 page

LAN9252

DS00001909A-page 142

 2015 Microchip Technology Inc.

11.2.15

REQUIRED ETHERNET MAGNETICS (100BASE-TX)

The magnetics selected for use with the device should be an Auto-MDIX style magnetic, which is widely available from

several vendors. Please review the SMSC/Microchip Application note 8.13 “Suggested Magnetics” for the latest quali-

fied and suggested magnetics. A list of vendors and part numbers are provided within the application note.

11.2.16

PHY REGISTERS

PHYs A and B are comparable in functionality and have an identical set of non-memory mapped registers. These reg-

isters are indirectly accessed through the MII Management Control/Status Register, PHY Address Register, PHY Reg-

ister Address Register, PHY DATA Register, MII Management ECAT Access State Register, and MII Management ECAT

Access State Register.

Because PHY A and B registers are functionally identical, their register descriptions have been consolidated. A lower-

case “x” has been appended to the end of each PHY register name in this section, where “x” hold be replaced with “A”

or “B” for the PHY A or PHY B registers respectively. In some instances, a “1” or a “2” may be appropriate instead.

A list of the MII serial accessible Control and Status registers and their corresponding register index numbers is included

in Table 11-11. Each individual PHY is assigned a unique PHY address as detailed in Section 11.1.1, "PHY Addressing,"

on page 120.

In addition to the MII serial accessible Control and Status registers, a set of indirectly accessible registers provides sup-

port for the IEEE 802.3 Section 45.2 MDIO Manageable Device (MMD) Registers. A list of these registers and their cor-

responding register index numbers is included in Table 11-14.

Control and Status Registers

Table 11-11 provides a list of supported registers. Register details, including bit definitions, are provided in the following

subsections.

Unless otherwise specified, reserved fields must be written with zeros if the register is written.

TABLE 11-10: 100BASE-FX LOS, SD AND TP COPPER SELECTION PHY B

FXLOSEN

FXSDENB

PHY Mode

<1 V (typ.)

TP copper

>1 V (typ.)

100BASE-FX Signal Detect

>2 V (typ.)

n/a

100BASE-FX LOS

TABLE 11-11: PHY A AND B MII SERIALLY ACCESSIBLE CONTROL AND STATUS REGISTERS

Index

Group

PHY x Basic Control Register (PHY_BASIC_CONTROL_x)

Basic

PHY x Basic Status Register (PHY_BASIC_STATUS_x)

Basic

PHY x Identification MSB Register (PHY_ID_MSB_x)

Extended

PHY x Identification LSB Register (PHY_ID_LSB_x)

Extended

PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)

Extended

PHY x Auto-Negotiation Link Partner Base Page Ability Register

(PHY_AN_LP_BASE_ABILITY_x)

Extended

PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x)

Extended

PHY x Auto Negotiation Next Page TX Register (PHY_AN_NP_TX_x)

Extended

PHY x Auto Negotiation Next Page RX Register (PHY_AN_NP_RX_x)

Extended

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