PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

19

Interface Timing

Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.

BCK

LRCK

DOUT

t(BCKH)

t(BCKL)

t(LRHD)

t(LRCP)

t(LRSU)

t(BCKP)

t(CKDO)

t(LRDO)

1.4 V

1.4 V

0.5 VDD

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150

ns

t(BCKH)

BCK pulse duration, HIGH

60

ns

t(BCKL)

BCK pulse duration, LOW

60

ns

t(LRSU)

LRCK setup time to BCK rising edge

20

ns

t(LRHD)

LRCK hold time to BCK rising edge

20

ns

t(LRCP)

LRCK period

10

µs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

10

ns

tf

Fall time of all signals

10

ns

NOTE: Timing measurement reference level is (VIH + VIL) / 2. Rise and fall times are measured

from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)