PCM1850

PCM1851

SLES108 − MARCH 2004

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24

Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address with read/write bit, data if

write or acknowledgement if read, and stop condition. The PCM1851 supports only slave receivers, so the R/W bit must

be set to 0.

9

SDA

SCL

St

1−7

8

1−8

9

1−8

9

9

Sp

Slave Address

ACK

DATA

ACK

DATA

ACK

ACK

R/W

R/W: Read Operation if 1; Otherwise, Write Operation

ACK: Acknowledgement of a Byte if 0

DATA: 8 Bits (Byte)

Stop

Condition

Start

Condition

Transmitter

M

M

M

S

M

S

M

S

S

M

Data Type

St

Slave Address

R/W

ACK

DATA

ACK

DATA

ACK

ACK

Sp

M: Master Device

S: Slave Device

St: Start Condition

Sp: Stop Condition

Figure 30. Basic I2C Framework

Write Operation

The PCM1851 has only the write mode. A master can write to any PCM1851 registers using single or multiple accesses.

The master sends a PCM1851 slave address with a write bit, a register address, and the data. If multiple access is required,

the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the

index register is incremented by 1 automatically. When the index register reaches 33h, the next value is 31h. When

undefined registers are accessed, the PCM1851 does not send an acknowledgement. Figure 31 is a diagram of the write

operation. The register address and the write data are 8 bits and MSB-first format.

Transmitter

M

MM

S

MS

M

M

Data Type

St

Slave Address

W

ACK

Reg Address

ACK

Write Data 1

Sp

S

M

ACK

Write Data 2

S

ACK

S

ACK

M: Master Device

S: Slave Device

St: Start Condition

Sp: Stop Condition

W: Write

ACK: Acknowledge

Figure 31. Framework for Write Operation