PCM1850

PCM1851

SLES108 − MARCH 2004

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14

POWER-ON RESET SEQUENCE

The PCM1850/1851 has an internal power-on reset circuit, and initialization (reset) is performed automatically at the time

that the power supply (VDD) exceeds 2.2 V (typ). While VDD < 2.2 V (typ) and for 1024 system clocks after VDD > 2.2 V (typ),

the PCM1850/1851 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset

state is released and the time of 4500/fS has passed. At the moment of the power-on reset release, the PCM1850/1851

does not need a system clock. Figure 21 illustrates the internal power-on reset timing and the digital output for power-on

reset.

System Clock

2.6 V

2.2 V

1.8 V

Internal Reset

DOUT

Zero Data

Normal Data

Reset

VDD

Release From Reset

1024 System Clocks

4500/fS

Figure 21. Internal Power-On Reset Timing