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PCM1850 데이터시트(PDF) 25 Page - Texas Instruments |
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PCM1850 데이터시트(HTML) 25 Page - Texas Instruments |
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25 / 34 page ![]() PCM1850 PCM1851 SLES108 − MARCH 2004 www.ti.com 25 TIMING DIAGRAM SDA SCL t(BUF) t(D-SU) t(D-HD) Start t(LOW) t(S-HD) t(SCL-F) t(SCL-R) t(HI) Repeated Start t(RS-SU) t(RS-HD) t(SDA-F) t(SDA-R) t(P-SU) Stop SYMBOL PARAMETER MIN MAX UNIT f(SCL) SCL clock frequency 100 kHz t(BUF) Bus free time between STOP and START condition 4.7 µs t(LOW) Low period of the SCL clock 4.7 µs t(HI) High period of the SCL clock 4 µs t(RS-SU) Setup time for START/repeated START condition 4.7 µs t(S-HD) t(RS-HD) Hold time for START/repeated START condition 4 µs t(D-SU) Data setup time 250 ns t(D-HD) Data hold time 0 900 ns t(SCL-R) Rise time of SCL signal 20 + 0.1CB 1000 ns t(SCL-F) Fall time of SCL signal 20 + 0.1CB 1000 ns t(SDA-R) Rise time of SDA signal 20 + 0.1CB 1000 ns t(SDA-F) Fall time of SDA signal 20 + 0.1CB 1000 ns t(P-SU) Setup time for STOP condition 4 µs CB Capacitive load for SDA and SCL line 400 pF VNH Noise margin at HIGH level for each connected device (including hysteresis) 0.2 VDD V Figure 32. PCM1851 Control Interface Timing Requirements |
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