PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

28

BOARD DESIGN AND LAYOUT CONSIDERATIONS

VCC, VDD Pins

The digital and analog power supply lines to the PCM1850/1851 must be bypassed to the corresponding ground pins with

0.1-

µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance

of the ADC.

AGND, DGND Pins

To maximize the dynamic performance of the PCM1850/1851, the analog and digital grounds are not connected internally.

These grounds must have low impedance to avoid digital noise feeding back into the analog ground. Therefore, they should

be connected directly to each other under the parts to reduce the potential of a noise problem.

VINL[1:6], VINR[1:6] Pins

A 0.33-

µF capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency. If higher

full-scale input voltage is required, it can be adjusted by adding only one series resistor to each VINxx pin, but a signal source

resistance less than 1 k

Ω is recommended for these pins in order to keep accuracy of the gain control command and to

maintain crosstalk performance.

MOUTL, MOUTR Pins

An ac-coupled light load is recommended; a 2.2-

µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.

VREF1, VREF2, VREFS Pins

Between VREF1 and AGND, VREF2 and AGND, and VREFS and AGND, 0.1-µF ceramic and 10-µF electrolytic capacitors

are recommended to ensure low source impedance of the ADC references. These capacitors should be located as close

as possible to the VREF1, VREF2, and VREFS pins to reduce dynamic errors on the ADC references. The differential voltage

between VREF2 and AGND sets the analog input full-scale range.

BCK and LRCK Pins (in Master Mode), DOUT Pin

These pins have enough load driving capability. However, if the output line is long, locating a buffer near the PCM1850/1851

and minimizing load capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the

dynamic performance of the ADC.

System Clock

Because the PCM1850/1851 operates based on a system clock, the quality of the system clock can influence dynamic

performance. Therefore, it is recommended to consider the system clock duty, jitter, and the time difference between the

system clock transition and the BCK or LRCK transition in slave mode.