SLAS366 datasheet(16/58 Pages) TI2

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3–4

3.3.4

Analog Output

The OUTP1 and OUTM1 are differential output from the DAC channel. The OUTP1 and OUTM1 can drive a load of

600-

Ω directly and be either differential or single-ended (see Figure 3–4).

OUTP1

OUTM1

Differential Output OUTP/OUTM

OUTP1

OUTM1

Single-Ended Output OUTP/OUTM

Figure 3–4. OUTP1/OUTM1 Output

3.4

IIR/FIR Control

3.4.1

Overflow Flags

The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog signal

has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an overflow flag

(bit D4) of control register 1 indicating that the digital input has exceeded the range of internal interpolation filter

calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user reads the register.

Reading this value resets the overflow flag. These flags need to be reset after power-up by reading the register. If

FIR/IIR overflow occurs, the input signal is attenuated by either the PGA or some other method.

3.4.2

IIR/FIR Bypass Mode

An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This mode

is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to four times

normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8 kHz) with IIR/FIR,

if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4

×8 kHz = 32 kHz. The sinc filters of the two paths

can not be bypassed. A maximum of eight devices in cascade can be supported in the IIR/FIR bypassed mode.

In this mode , the ADC channel outputs data which has been decimated only till 4Fs. Similarly DAC channel input

needs to be pre-interpolated to 4Fs before being given to the device. This mode allows users the flexibility to

implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR Bypass

mode.

3.5

System Reset and Power Management

3.5.1

Software and Hardware Reset

The TLV320AIC14 resets internal counters and registers in response to either of two events:

•

A low-going reset pulse is applied to terminal RESET

•

A 1 is written to the programmable software reset bits (D3 of control register 3)

NOTE:The TLV320AIC14 requires a power-up reset applied to the RESET pin.

Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active low)

signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC14 enters the

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