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SLAS366 데이터시트(PDF) 42 Page - Texas Instruments |
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SLAS366 데이터시트(HTML) 42 Page - Texas Instruments |
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42 / 58 page ![]() 5–6 5.11 Timing Requirements (see Parameter Measurement Information) TEST CONDITIONS MIN TYP MAX UNIT twH Pulse duration, MCLK high 5 twL Pulse duration, MCLK low 5 tsu1 Setup time, RESET, before MCLK high (see Figure 5–1) 3 th1 Hold time, RESET, after MCLK high (see Figure 5–1) 2 td1 Delay time, SCLK ↑ to FS/FSD↓ CL = 20 pF 5 ns td2 Delay time, SCLK ↑ to FS/FSD↑ 5 td3 Delay time, SCLK ↑ to DOUT 15 ten Enable time, SCLK ↑ to DOUT 15 tdis Disable time, SCLK ↑ to DOUT 15 tsu2 Setup time, DIN, before SCLK ↓ 10 th2 Hold time, DIN, after SCLK ↓ 10 th1 2.4 V MCLK RESET 2.4 V tsu1 2.4 V twL twH Figure 5–1. Hardware Reset Timing td1 td2 td1 td2 ten td3 tdis tsu2 th2 D15 D15 SCLK FS FSD DOUT DIN Figure 5–2. Serial Communication Timing NOTE: Above Figures are meant to show timing delays only. |
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