SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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The 32-bit shift register at the bottom is used to shift in TDI_SM directly in normal mode or to shift in TMS_SM or

TDO_SM in the loop-back mode. After each long word of 32 bits is shifted into this register, the contents of the

register are transferred to the corresponding TDI memory location before the next shift operation.

SHIFTER IMPLEMENTATION

Shift register implementation is illustrated in Figure 6. Shift out enable for the TMS_SM and TDO_SM shifters is

generated by comparing the clock pulse counter output to the clock divider - 1. Shift in enable for the TDI_SM

shifter is generated by comparing the clock pulse counter to the programmable divisor/2 - 1. These enables are

gated by the control signals from SSIC so that data are shifted out (TMS_SM/TDO_SM) or shifted in (TDI_SM)

only when necessary.

Figure 6. Shift Register Implementation and Timing

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