SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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SCANSTA101 ARCHITECTURE

Figure 1. SCANSTA101 STA Master and Interfaces

Figure 1 shows a high level view of the SCANSTA101 STA Master and its interfaces. Table 1 provides a brief

description of each of these interfaces. provides a brief description of the device pins and their functions. The

device is composed of three interfaces around a dual-port memory. These interfaces are the Parallel Processor

Interface (PPI), Serial Scan Interface (SSI), and Test and Debug Interface. The System Input block designates

inputs that have global use across the device.

The Test and Debug Interface supports BIST, boundary scan, and internal scan for the SCANSTA101.

Table 1. INTERFACE DESCRIPTIONS

Interface

Description

Parallel Processor Interface

Used for configuration, ScanMaster scan chain loads and reads, programmable device file loads

and reads, and status monitoring.

Serial Scan Interface

Performs parallel to serial conversion, sequences and formats the outgoing serial stream to

conform to 1149.1 protocol.

Test and Debug Interface

IEEE 1149.1 TAP

System Inputs

Interface inputs for system control, i.e. clock, reset and output tristate control.

2

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