SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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Figure 15. SSI Timing Diagram with Clock Divider set to 8

Table 16. SCANSTA101 1149.1 Signal Descriptions

No. of

Signal Name

Pin Type

Driver Type

Freq. MHz

Description

Bits

TDO

1

O

LVTTL

up to 25

SCANSTA101 Test Data Out

TDI

1

I,U

LVTTL

up to 25

SCANSTA101 Test Data In (pullup (U))

TMS

1

I,U

LVTTL

up to 25

SCANSTA101 Test Mode Select (pullup (U))

TCK

1

I

LVTTL

up to 25

SCANSTA101 Test Clock

TRST

1

I,U,H

LVTTL

N/A

SCANSTA101 Test Reset (pullup (U) & hysteresis (H))

SAFE MODE

This device implements the following design rules to provide Single Event Upset/Single Event Error (SEU/SEE)

protection:

•

Triple modular redundancy (TMR) for TRST0_SM and TRST1_SM outputs with the help of a TMR D flip-flop .

•

After reset all scan interface outputs are driven to SEU tolerant safe values as shown below:

–

TMS_SM = 1

–

TCK_SM = 0

–

TDO_SM = high-Z

–

TRST0_SM = 0

–

TRST1_SM = 0

•

The EXTEST and the HIGHZ outputs from the JTAG TAP controller are gated with TRST to protect the

boundary scan cells from inadvertently entering the test mode.

CLOCK GENERATION AND DISTRIBUTION

Input Clock (SCK): Up to 66 MHz

Output Clock (TCK_SM): TCK_SM is a divided, registered version of SCK.

•

Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of SCK.

•

Frequency: up to 25 MHz

24

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