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SCANSTA101SM/NOPB 데이터시트(PDF) 7 Page - Texas Instruments

부품명 SCANSTA101SM/NOPB
상세설명  SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master
PDF  42 Pages
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SCANSTA101
www.ti.com
SNLS057J – MAY 2002 – REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω
unless otherwise specified.
Symbol
Parameter
Conditions
# of SCK
Min
Max
Units
(1) (2)
tD3
Propagation Delay
Output data valid to DTACK low, all read
See Figure 13
1
ns
cycles
tpHL1
Propagation Delay
10.5
STB low to INT low, register write (clears
See Figure 12
5 or 6
ns
Interrupt)
tW
Clock Pulse Width, SCK, H or L
3.0
ns
fMAX
Clock Frequency, SCK
66
MHz
tRELEASE
Release Time, RST to STB
2
ns
Symbol
Parameter
Conditions
Min
Max
Units
SERIAL SCAN INTERFACE (SSI)
tD5
Propagation Delay
See Figure 14
11.5
ns
SCK to TCK_SM
tD6
Propagation Delay
See Figure 14
12.0
ns
SCK to TDO_SM
tD7
Propagation Delay
See Figure 14
12.5
ns
SCK to TMS_SM
tD8
Propagation Delay - tpLH
See Figure 14
15.0
ns
SCK to TRIST_SM
tD9
Propagation Delay - tpHL
See Figure 14
12.5
ns
SCK to TRIST_SM
tD10
Propagation Delay
See Figure 14
12.5
ns
SCK to TDO_SM disable
tD11
Propagation Delay
See Figure 14
14.0
ns
SCK to TDO_SM enable
tEN1
Enable Delay
See Figure 14
12.0
ns
OE low to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
tDIS1
Disable Delay
See Figure 14
11.0
ns
OE high to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
tEN2
Enable Delay
10.0
ns
OE low to TRIST_SM
tDIS2
Disable Delay
11.5
ns
OE high to TRIST_SM
tDIS3
Disable Delay
12.5
ns
RST low to TRST0_SM
tS2
Setup Time
See Figure 14
3.5
ns
SCK to TDI_SM
tH2
Hold Time
See Figure 14
2.0
ns
SCK to TDI_SM
TEST & DEBUG INTERFACE TIMING REQUIREMENTS (SCAN)
tS
Setup Time
2.0
ns
TMS to TCK
tH
Hold Time
1.0
ns
TMS to TCK
tS
Setup Time
1.0
ns
TDI to TCK
tH
Hold Time
2.0
ns
TDI to TCK
tW
Pulse Width
10.0
ns
TCK (H or L)
Copyright © 2002–2013, Texas Instruments Incorporated
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