SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

Table 3. MEMORY/REGISTER ADDRESS MAP (continued)

A4

A3

A2

A1

A0

Function

Base Address

Long Word

Structure/Size

Index

0

1

1

1

1

Expected

0 x 380

0 - 0x1BF

See (3)

1

0

0

0

0

Mask

0 x 540

0 - 0x1BF

See (3)

1

0

0

0

1

Vector Index

N/A

N/A

16-bit Register

1

0

0

1

0

Vector 1

0 x 700

0x0 - 0x1

See (4), Table 4

Vector 2

0 x 700

0x2 - 0x3

Vector 3

0 x 700

0x4 - 0x5

Vector 4

0 x 700

0x6 - 0x7

1

0

0

1

1

Header/Trailer Index

N/A

N/A

16-bit Register

1

0

1

0

0

Data Header

0 x 708

0x0 - 0x1F

See Table 5

Data Trailer

0 x 728

0x20 - 0x3F

Instruction Header

0 x 748

0x40 - 0x5F

Instruction Trailer

0 x 768

0x60 - 0x7F

1

0

1

0

1

Macro Index

N/A

N/A

16-bit Register

1

0

1

1

0

Macro 1

0 x 788

0x0

See Table 6,

Table 7 and

Macro 2

0 x 789

0x1

Table 8

Macro 3 . . .

0 x 78A . . .

0x2 . . .

Macro 16

0 x 797

0xF

1

0

1

1

1

Sequencer Index

N/A

N/A

16-bit Register

1

1

0

0

0

Sequencer

0 x 798

0x0 - 0x1F

See Table 9

1

1

0

0

1

Scan Bridge Support Index

N/A

N/A

16-bit Register

1

1

0

1

0

Scan Bridge Support

0 x 7B8

0x0 - 0x3F

See Table 10

(4)

The upper two bytes of each vector are ignored. These have been inserted to make the space align on long word boundaries.

Table 4. VECTOR STRUCTURE

Bit(s)

Function

0x00 - 0x1F

Length (maximum of 4G)

0x20 - 0x27

Macro Number (1 of 256) Room for scaleability

0x28 - 0x2E

Reserved

0x2F

Preloaded data / Load-on-the-fly (LotF)

0x30 - 0x3F

Reserved

Table 5. HEADER/TRAILER STRUCTURE

Bit(s)

Function

0x00 - 0x1F

32-bit count (1)

0x20 - 0x3FF

124 bytes (992 bits) header/trailer data

(1)

Count must be greater than zero if the Header/Trailer Usage bits are not equal to "000" or "111".

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