ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VA = VD = VP = VDR = 3.3V, fCLK = 200 MHz, fIN = 50 MHz, PLL & Buffer bypassed, TA = 25°C, unless otherwise stated

SINAD vs. CLK Duty Cycle

SFDR vs. Supply Voltage

Figure 32.

Figure 33.

SFDR vs. Input Frequency

SFDR vs. Temperature

Figure 34.

Figure 35.

SFDR vs. Sample Rate

SFDR vs. Clock Duty Cycle

Figure 36.

Figure 37.

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