ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

POWER SUPPLY CONSIDERATIONS

It is important to note that capacitors have an equivalent series inductance associated with them such that,

beyond a certain frequency, the capacitor behaves more like an inductance than a capacitance and adequate

bypassing may be infective, resulting in the power distribution system having a high impedance, which could

further result in excessive noise on the power supply. The frequency beyond which adequate bypassing may be

effective depends primarily upon the chemistry of the capacitor dielectric, but can also vary a little from one

manufacturer to another. Even so, this frequency is in the hundreds of Megahertz. Note, however, that a 200

MHz clock will have significant harmonic energy far beyond this. The result could be high frequency noise on the

supply lines that could effect the SNR performance of the converter.

The use of adjacent power and ground planes will go a long way toward reducing the impedance of the power

distribution system and is encouraged. Furthermore, we suggest placing the lowest value of bypass capacitor

close to the supply pin on the same side of the board as the ADC and connect the ground end of the bypass

capacitor to the ground plane with at least two through holes. The through holes have an inductance associated

with them and using two or more such holes puts these inductances in parallel, lowering the effective inductance

to ground.

Supply Voltages

The ADC8D200 will perform well with power supply voltages in the range specified in the Operating Ratings, just

before the Electrical Table. Many individual devices may perform well down to supply voltages of 2.7V, but this

should not be relied upon because part of the product distribution, depending upon normal fabrication process

tolerances, could result in the majority of some production runs not functioning well below 3.0V.

While all supplies may be of the same voltage, the digital supply (VD), the PLL supply (VP) and the output driver

supply (VDR) ADC08B200 should never be higher than 300 mV above the analog supply (VA). Furthermore, the

output driver supply, VDR may be as low as 2.7V only when using the buffer and when the buffer read clock

(RCLK) frequency is no higher than 50 MHz because the output slew rate decreases at low VDR voltages and the

output eye may not be open enough to allow reliable data capture.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single, unified

ground plane should be used. Do not split the ground plane.

Coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance that may seem impossible to isolate and remedy. The solution is to keep all lines separated from

each other by at least six times the height above the reference plane, and to keep the analog circuitry well

separated from the digital circuitry.

The DR GND connection to the ground plane should not use the same through holes used by other ground

connections. High power digital components should not be located near any analog components.

Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog

path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should

be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be

avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies

is obtained with a straight signal path.

The reference and analog inputs should be isolated from noisy signal traces to avoid coupling of spurious signals

into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and

ground should be connected to a very clean point in the ground plane and preferably with 2 to 4 closely spaced

through holes.

DYNAMIC PERFORMANCE

The ADC08B200 is a.c. tested and its dynamic performance is ensured. To meet the published specifications,

the clock source driving the CLK input must exhibit as little jitter as possible. For best a.c. performance, each

clock destination should be driven by a separate source, such as with a clock distribution chip or with a clock tree

such as seen in Figure 48.

Copyright © 2007–2013, Texas Instruments Incorporated

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