ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

The DRDY output should be have a load that is identical to the load of the digital data outputs to ensure that the

DRDY output edge transitions at the same time as does the data.

The WENSYNC Pin

This output is synchronous with the internal sample clock and is provided as an indication as to when sampling

takes place. The actual point in time when sampling takes place is as indicated in Figure 3.

The EF Pin

This Empty Flag goes high, synchronous with the internal sample clock, when the Capture Buffer is empty, either

by the buffer having been completely read or upon RESET of the device. This output goes low when one or more

bytes is written to the buffer. When EF goes high, the DRDY and Data outputs stop switching and both DRDY

and the Data lines remain low if OEDGE=1, or high if OEDGE=0.

The FF Pin

The Full Flag output indicates that the buffer is full and goes high, synchronous with the internal sample clock,

when the capture buffer is full. If the WEN input remains high, the rise of the next sample clock after the FF

output goes high will cause the buffer pointer to "wrap around" and start writing over the previous data unless the

ASW input is high. The FF signal goes low when the REN signal goes high and the full condition no longer

exists. This signal also goes low upon a RESET of the device.

CLOCK OPTIONS

The ADC08B200 incorporates a PLL to facilitate clocking. The PLL, like any PLL or DLL, can add phase noise to

the clock signal and so to the conversion process. The effect of this phase noise increases with higher analog

signal input frequencies. If a stable clock source at the desired sample rate is available, it is preferable to use

that clock as the sample clock for the ADC08B200, bypassing the PLL. If such a source is not available, the

internal PLL may be used to multiply the input clock frequency by 2, 4 or 8 to obtain the desired sample rate from

a lower frequency clock source.

Bypassing the PLL or setting the CLK frequency multiplier is accomplished through the use of the two MULT pins

as indicated in Table 1. Expected noise performance with and without the use of the PLL is indicated in TYPICAL

PERFORMANCE CHARACTERISTICS.

Table 1. MULT Pin Function

MULT1

MULT0

CLK Frequency Multiplier

CLK Frequency Range (MHz)

0

0

1

1 - 210

0

1

2

15 - 105

1

0

4

15 - 50

1

1

8

15 - 25

The internal sampling clock frequency is the input clock frequency at the CLK pin multiplied by the multiplier in

Table 1. When the PLL is bypassed, the input clock at the CLK pin is used as the sample clock and the PLL is

disabled.

USING THE DATA BUFFER

The Data Buffer has read and write pointers and the first word written to it is the first word read from it. The Data

Buffer is configurable to 256-, 512-, or 1024- bytes, and must be completely filled to the configured number of

bytes before it can be read. The "FF" flag goes high once the configured number of bytes is in the buffer are

read. Once the data buffer contents are completely read, indicated by the "EF" flag going high, the same data

cannot be read again. It is possible to read back only part of the buffer contents. Asserting the WEN high input,

even while a valid read operation is under way, will cause a resetting of the read and write pointers and initiation

of a write operation.

Copyright © 2007–2013, Texas Instruments Incorporated

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