MB85RC256TY(AEC-Q100 Compliant)

4

DS501-00077-1v1-E

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I2C COMMUNICATION PROTOCOL

The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A

data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.

The SDA signal should change while the SCL is the “L” level. However, as an exception, when starting and

stopping communication sequence, the SDA is allowed to change while the SCL is the “H” level.

• Start Condition

To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while

the SCL input is in the “H” level.

• Stop Condition

To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL

input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the

standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and

enters the standby state.

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Start Condition, Stop Condition

Note : At the write operation, the FeRAM device does not need the programming wait time (tWC) after issuing

the Stop Condition.

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ACKNOWLEDGE (ACK)

In the I2C bus, serial data including memory address or memory information is sent and received in units of

8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The

receiver side usually outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully

transmitted and received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this

9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z released period, the

receiver side pulls the SDA line down to indicate the “L” level that the previous 8 bits communication is

successfully received.

In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side

stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state

after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition

in this released bus state.



Acknowledge timing overview diagram

SCL

SDA

Start

Stop

H or L

SCL

123

89

SDA

Start

ACK

The transmitter side should always release SDA on the 9th bit.

At this time, the receiver side outputs a pull-down if the previous

8 bits data are received correctly (ACK response).