MB85RC256TY(AEC-Q100 Compliant)

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DS501-00077-1v1-E

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DATA STRUCTURE

In the I2C bus, the acknowledge “L” level is output on the 9th bit by a slave, after the 8 bits of the device

address word following the start condition are input by a master. After confirming the acknowledge response

by the master, the master outputs 8 bits  2 memory address to the slave. When the each memory address

input ends, the slave again outputs the acknowledge “L” level. After this operation, the I/O data follows in

units of 8 bits, with the acknowledge “L” level output after every 8 bits.

It is determined by the R/W code whether the data line is driven by the master or the slave. However, the

clock line shall be driven by the master. For a write operation, the slave will accept 8 bits from the master,

then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8 bits.

For a read operation, the slave will place 8 bits on the data line, then wait for an acknowledge from the master.

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FeRAM ACKNOWLEDGE -- POLLING NOT REQUIRED

The MB85RC256TY performs the high speed write operations, so any waiting time for an ACK polling* does

not occur.

*: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or

not. It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting

the start condition and then the device address word (8 bits) during rewriting.

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WRITE PROTECT (WP)

The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is

set to the “H” level, the entire memory array will be write protected. When the Write Protect pin is the “L”

level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or

“L” level.

Note : The Write Protect pin is pulled down internally to the VSS pin, therefore if the Write Protect pin is open,

the pin status is detected as the “L” level (write enabled).