MB85RC256TY(AEC-Q100 Compliant)

8

DS501-00077-1v1-E

• Current Address Read

When the previous write or read operation finishes successfully up to the stop condition and assumes the

last accessed address is “n”, then the address at “n+1” is read by sending the following command unless

turning the power off. If the memory address is last address, the address counter will roll over to (0000H).

The current address in memory address buffer is undefined immediately after the power is turned on.

• Random Read

The one byte of data from the memory address saved in the memory address buffer can be read out

synchronously to SCL by specifying the address in the same way as for a write, and then issuing another

start condition and sending the Device Address Word (R/W “1” input).

The final NACK (SDA is the “H” level) is issued by the receiver that receives the data. In this case, this bit

is issued by the master side.

A

S

P

N

S

A2 A1

A

N P

Read

Data 8bits

1

1

010

A0

Access from master

Access from slave

Start Condition

ACK(SDA is the “L” level)

Stop Condition

NACK(SDA is the “H” level)

A

S

P

N

S

A2 A1

A

A

A

P

Address

High 8bits

Address

Low 8bits

0

1

010

S

A2 A1

A

1

1

010

Read

Data 8bits

N

A0

A0

Access from master

Access from slave

Start Condition

ACK(SDA is the “L” level)

Stop Condition

NACK(SDA is the “H” level)