MB85RC256TY(AEC-Q100 Compliant)

10

DS501-00077-1v1-E

• Sleep Mode

MB85RC256TY provides Sleep mode which reduces less current consumption than Standby mode, by

stooping the internal regulator circuits. Following sequences enable the Sleep mode transition.

<Transition to Sleep mode>

a) The master sends start condition followed by F8h.

b) After ACK response from slave, the master sends the device address word.

In this device address word, Read/Write code is Don't care.

c) After ACK response from slave, the master re-sends the start condition followed by 86h.

d) The slave moves to Sleep mode after ACK response to the master.

Even if the MB85RC256TY stays in the Sleep mode, SDA and SCL signals are monitored. Following se-

quences enable the transition to Standby mode after recovery time (tREC) of internal regulator circuits.

<Exit from Sleep mode>

a) The master sends start condition followed by device address word.

In this device address word, Read/Write code is Don't care.

b) At the rising edge of 9th clock from start condition, an internal regulator starts to operate its recovery

sequence.

c) After the recovery time (tREC) passed, standby mode enabled.

After returning to Standby mode, reading and writing are enabled by sending each command starts with start

condition.

S 1 1 1

1 1 000

1 0 1

0 A2 A1

A S 1 0

0 0 011

A

0

R/W

AP

A

S

P

A0

Access from slave

Start Condition

Stop Condition

ACK(SDA is the “L” level)

Access from master

1 0 1

0 A2 A1

X

S

R/W

A

S

1 0 1

0 A2 A1

A

S

R/W

A0

A0

Access from slave

Start Condition

ACK(SDA is the “L” level)

Access from master

Recovery

operation

Start recovery operation