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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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L9679E 데이터시트(PDF) 103 Page - STMicroelectronics |
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L9679E 데이터시트(HTML) 103 Page - STMicroelectronics |
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103 / 127 page  Symbol Parameter Comments / Conditions Min Typ Max Unit Note ILKG_SS_2CH_ARMED SSxy leakage current Device ON SSxy ≤ 35 V SFx = SFy = 0 Total SSxy leakage current with both x and y channels armed (= 2* 490 µA) plus 30 µA due to 600 KOhm between ESD SQUIB/ PYROSWITCH rail and ground. Assuming all SSxy at the same voltage. Not Tested 800 1010 1230 µA - ILKG_SF_ON_0V SF leakage current Device ON, VSYNC = SSxy = 35 V, SFx = 0 V -5 - 5 µA - ILKG_SF_ON_35V SF leakage current Device ON, VSYNC = SSxy = 35 V, SFx = 35 V -5 - 50 µA - ILKG_SF_OFF_0V SF leakage current Device OFF VSYNC = open, SSxy = open but all SSxy pins connected, SFx = 0V -5 - 5 µA - ILKG_SF_OFF_35V SF leakage current Device OFF VSYNC = open, SSxy = open but all SSxy pins connected, SFx = 35 V -5 - 50 µA - ILKG_SR_ON SR leakage current Device ON, VSYNC = SSxy = 35 V, SRx = 0 V-35 -5 - 50 µA - ILKG_SR_OFF SR leakage current DEVICE OFF, VSYNC=open, SSxy = open but all SSxy pins connected, SRx pull down current OFF SRx = 0 V-20V -5 - 50 µA - ILKG_SR_OFF_H SR leakage current_H DEVICE OFF, VSYNC=open, SSxy = open but all SSxy pins connected, SRx pull down current OFF SRx = 35 V -5 - 30 mA - VSR_CLAMP SR voltage clamp 35 - 40 V - LDEPL Load inductance Design info 0 - 56 µH Maximum load inductance(2) CSFx Load capacitance Maximum capacitance to GND Design info 13 - 455 nF - CSRx Load capacitance Maximum capacitance to GND Design info 13 - 455 nF - CSSxy SSxy capacitance Maximum capacitance to GND connected directly to SSxy pin Design info - - 10 nF - RSFLx Load impedance Design info - - 6.5 Ω - - Wire length Squib/Pyroswitch Loops containing a clock spring shall be limited to a maximum length of 3m 1 10 m - RWirex Wire resistance Design info 16.8 63.4 mΩ/m - LWirex Wire Inductance Design info 0.6 1.8 µH/m - RCSx Clock spring resistance Maximum number of clock springs is 3 for any IC Design Info 0 0.7 Ω LCSx Clock spring inductance Design Info 0 42.9 µH kL CS1 – LCS2 Clock spring coupling Design Info 0.739 0.903 LEMI Squib/Pyroswitch EMI protection Design Info 0 7.7 µH 1. In case of an unsupplied device and shorted deployment pins (e.g. to battery voltage), the dynamic reverse current through the high side power stage depends on CSSxy. 2. see LDEPL calculation L9679E Electrical characteristics DS12485 - Rev 8 page 103/127 |
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