전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

PESDXV4UG 데이터시트(PDF) 9 Page - NXP Semiconductors

부품명 PESDXV4UG
상세설명  Very low capacitance unidirectional quadruple ESD protection diode arrays
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

PESDXV4UG 데이터시트(HTML) 9 Page - NXP Semiconductors

Back Button PESDXV4UG Datasheet HTML 5Page - NXP Semiconductors PESDXV4UG Datasheet HTML 6Page - NXP Semiconductors PESDXV4UG Datasheet HTML 7Page - NXP Semiconductors PESDXV4UG Datasheet HTML 8Page - NXP Semiconductors PESDXV4UG Datasheet HTML 9Page - NXP Semiconductors PESDXV4UG Datasheet HTML 10Page - NXP Semiconductors PESDXV4UG Datasheet HTML 11Page - NXP Semiconductors PESDXV4UG Datasheet HTML 12Page - NXP Semiconductors PESDXV4UG Datasheet HTML 13Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 16 page
background image
PESDXV4UF_G_W_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 January 2008
9 of 16
NXP Semiconductors
PESDxV4UF/G/W
Very low capacitance quadruple ESD protection diode arrays
7.
Application information
The devices are designed for the protection of up to four unidirectional data or signal lines
from the damage caused by ESD and surge pulses. The devices may be used on lines
where the signal polarities are both, positive and negative with respect to ground. The
devices provide a surge capability of 16 W per line for an 8/20
µs waveform each.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
Fig 9.
Application diagram
006aab126
data- or transmission lines
n.c.
unidirectional protection of 4 lines
DUT
1
2
3
5
4
bidirectional protection of 3 lines
DUT
1
2
3
5
4



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com