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IS25LE01G-RILA3 데이터시트(PDF) 91 Page - Integrated Silicon Solution, Inc

부품명 IS25LE01G-RILA3
상세설명  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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제조업체  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3 데이터시트(HTML) 91 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
91
Rev. A6
01/14/2025
8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K/256K:D8h or
4BER64K/256K:DCh)
A Block Erase (BER) instruction erases a 32/64 or 32/256 Kbyte block. Before the execution of a BER instruction,
the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
• 52h/D8h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
• 52h/D8h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
• 5Ch/DCh is followed by a 4-byte address (A31-A0)
The BER instruction code and three or four address bytes as above are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control
logic automatically handles the erase voltage and timing.
Figure 8.31 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=0], 3-byte address)
Instruction = D8h
23
CE #
SCK
SI
3
2
SO
1
0
3-byte Address
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
Mode 3
Mode 0
Figure 8.32 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=1] or DCh, 4-byte address)
31
4-byte Address
29
28
36
37
38
39
Instruction = D8h/DCh
CE #
SCK
SI
3
2
SO
1
0
High Impedance
...
0
1
2
3
4
5
6
7
8
9
10
...
Mode 3
Mode 0



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