IS25LE01G-RILA3 datasheet(94/186 Pages) ISSI

부품명	IS25LE01G-RILA3

상세설명	SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	186 Pages

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제조업체	ISSI [Integrated Silicon Solution, Inc]

홈페이지	http://www.issi.com

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94 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

01/14/2025

8.15 CHIP ERASE OPERATION (CER, C7h/60h)

A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after

completion of a chip erase operation.

The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,

otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase

voltage and timing.

Chip Erase (CER) instruction can be executed only when Block Protection (BP3~BP0) bits are set to 0s. If the BP

bits are not 0, the CER command is not executed and E_ERR and PROT_E are set.

Chip Erase (CER) instruction will skip sectors/blocks protected by ASP (DYB bits or PPB bits) and will not set

E_ERR and PROT_E if sectors/blocks are protected by ASP only.

Figure 8.39 Chip Erase Sequence In SPI Mode

Instruction = C7h/60h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.40 Chip Erase Sequence In QPI Mode

C7h/60h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LE01G-RILA3 데이터시트(PDF) 94 Page - Integrated Silicon Solution, Inc