STM32H533CE datasheet(81/231 Pages) STMICROELECTRONICS

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139

PB8

I/O

FT_fsh

TIM4_CH3, I3C1_SCL, I2C1_SCL,

SPI4_RDY, SPI3_NSS/I2S3_WS,

SDMMC1_CKIN, UART4_RX,

FDCAN1_RX, SDMMC1_D4,

DCMI_D6/PSSI_D6, EVENTOUT

140

PB9

I/O

FT_fsh

TIM4_CH4, I3C1_SDA, I2C1_SDA,

SPI2_NSS/I2S2_WS,

SPI3_SCK/I2S3_CK, SDMMC1_CDIR,

UART4_TX, FDCAN1_TX, SDMMC1_D5,

DCMI_D7/PSSI_D7, EVENTOUT

141

PE0

I/O

FT_h

LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2,

LPTIM2_ETR, SPI3_RDY, FDCAN1_RX,

FMC_NBL0, DCMI_D2/PSSI_D2,

EVENTOUT

142

VCAP

143

VSS

100

144

VDD

VDDIO2

1. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer

(VREFBUF) is not available and must be kept disabled.

2. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current, the use of PC13 to PC15 GPIOs in output

mode is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).

3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the

system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.

4. As a tamper input, only PC13, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, and PA1 are functional in Standby and VBAT

mode

5. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are

activated too.

Table 14. STM32H533xx pin/ball definition (continued)

Pin number(1)

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