STM32H533CE datasheet(26/231 Pages) STMICROELECTRONICS

26 / 231 page

Functional overview

STM32H533xx

26/231

DS14539 Rev 1

3.9.2

Default TrustZone security state

The default system security state is detailed below:

•

CPU:

–

Cortex-M33 is in secure state after reset. The boot address must be in secure

address.

•

Memory map:

–

SAU is fully secure after reset. Consequently, all memory map is fully secure. Up

to eight SAU configurable regions are available for security attribution.

•

Flash memory:

–

Flash memory security area is defined by watermark user options.

–

Flash memory block based area is non-secure after reset.

•

SRAMs:

–

All SRAMs are secure after reset. MPCBB (memory protection block based

controller) is secure.

•

External memories:

–

FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection

watermark based controller) is secure.

•

Peripherals

–

Securable peripherals are non-secure after reset.

–

TrustZone-aware peripherals are non-secure after reset. Their secure

configuration registers are secure.

•

All GPIOs are secure after reset.

•

Interrupts:

–

NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-

secure state.

•

TZIC: All illegal access interrupts are disabled after reset.

3.10

Power supply management

The power controller (PWR) main features are:

•

Power supplies and supply domains

–

Core domain (VCORE)

–VDD domain

–

Backup domain (VBAT)

–

Analog domain (VDDA)

–

VDDIO2 domain

–

VDDUSB for USB transceiver

•

System supply voltage regulation

–

Voltage regulator (LDO)

•

Power supply supervision

–

POR/PDR monitor

–

BOR monitor

–PVD monitor

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